XRD98L63 Datasheet, PDF (8/41 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L63
SERIAL INTERFACE
The XRD98L63 uses a three wire serial interface
(LOAD, SDI & SCLK) to access the programmable
features and controls of the chip. The serial interface
uses a 16-bit shift register. The first 6 bits shifted in are
the address bits, the next 10 bits are the data bits. The
address bits select which of the internal registers will
receive the 10 data bits.
The interface will only load data from the shift register
into the register array if there are exactly 16 rising edges
of SCLK while LOAD is low. If more or less rising edges
are present, the data is discarded. There is no checking
of the address bits to ensure a valid register is written
to. If the address bits select an undefined register, the
LOAD
data will be discarded. There is a readback function
(see the Serial Interface Read Back section) that
outputs the contents of a selected register on pins
DB[11:2] of the digital output bus.
The following is the procedure for writing to the serial
interface:
1) Force LOAD pin low to enable shift register.
2) Shift in 16 bits, 6 address bits (msb first),
followed by 10 data bits (msb first).
3) Force LOAD pin high to transfer data from the
shift register to the serial interface register array.
Note: There must be exactly 16 rising edges of
SCLK while LOAD is low.
SCLK
t_set
SDI
t_L1
t_SCLK
t_L2
t_hold
MSB
LSB
A5
A4
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t1
t2
…
Figure 4. Serial Interface Timing Diagram
t15
t16 ^Time
SDI
SCLK
LSB
Data Bits
MSB
Address Bits
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 A0 A1 A2 A3 A4 A5
LOAD
Rev.1.01
Data Input
Register Array
Register
Select
Read Back
Output Bus
Figure 5. Serial Interface Block Diagram
8
Address
Decoder
to DB[11:2]