XRD98L63 Datasheet, PDF (25/41 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L63
Reset Reject
In the default state, the reset reject switches (φ3) are
always ON; they are not clocked. The reset pulse of
each pixel is transmitted to the first stage of the PGA.
Depending on the PGA gain and the actual voltage
level of the reset pulse, this could cause the first stage
of the PGA to rail. During the Black Level sampling, the
PGA should have enough time to recuperate, but as a
precaution, we have included the Reset Reject option.
When RSTreject = 1, the reset reject switches are
turned OFF at the end of the SPIX pulse and turned ON
again at the start of the SBLK pulse. This will effec-
tively reject the reset pulse and prevent it from railing
the PGA.
CCD Signal
SBLK
SPIX
ADCLK
φ3
Black Level
Video
Level
Reset Reject
Switches Turn OFF
Figure 19. Pixel Rate Clock Timing with RSTreject=1
Rev.1.01
25