XRD98L63 Datasheet, PDF (22/41 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L63
TIMING: CLOCK BASICS
There are 8 clock signals SBLK, SPIX, ADCLK,
CLAMP, CAL, PBLK, EOS and Fsync.
The pixel rate clocks are SBLK, SPIX, and ADCLK.
SBLK controls sampling of the Black reference level
for each pixel. SPIX controls sampling of the Video
level for each pixel. ADCLK controls the ADC sampling
of the PGA output and ADC operation.
The line rate clocks are CLAMP, CAL, PBLK and EOS.
CLAMP controls the DC restore function for the exter-
nal AC coupling capacitors. CAL controls the Black
level calibration by defining the OB pixels at the start
or end of each line. In the One Shot mode (CAL only),
CLAMP is not used. PBLK is used to disconnect the
CDS from the CCDin & REFin pins during vertical shift
time. If the DOclamp bit in the Clock register is high,
PBLK will also force the digital output bus, DB[11:0], to
output the value in the Offset register, OB[7:0]. EOS
is used in the Multiple Gain mode to indicate if a line (or
field) is even or odd.
Pipeline Delay
The digital outputs, DB[11:0] and OVER, are synchro-
nized to ADCLK. When ADCLKpol=0 (default), the
digital outputs change on the rising edge of ADCLK.
Figure 14 shows the pipeline delay (latency) from
sampling a pixel at the CDS input, until the correspond-
ing data is available at the digital output.
Clock Polarity
Each of the 8 clock pins has a separate polarity control
bit in the Polarity register. If the polarity bit for a clock
is low, then the clock is active low. If the polarity bit for
a clock is high, then the clock is active high. After reset
(by POR, Reset bit or XRESET pin), all clocks default
to active low; EOS defaults to active high.
SBLK
SPIX
ADCLK
CLAMP
CAL
PBLK
EOS
Fsync
Polarity
Aperture
Delays
Clock
Logic
AFE
ADC
Calibration
Figure 15. Clock Polarity & Aperture Delays
CCD
Signal
Pixel N
Black Level
Video
Level
Pixel N+1
sample
black
SBLK
SPIX
sample
video
ADCLK
sample
sample PGA2out
PGA1out
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
DB[11:0]
Pixel N-8
Pixel N-7
Pixel N-6
Pixel N-5
Pixel N-4
7.5 Pixel Pipeline Delay
Pixel N-3
bit 3
bit 2
error
bits 1&0 correction
Pixel N-2
t_DL
Pixel N-1
Pixel N
Rev.1.01
Figure 14. Pixel Timing Showing Pipeline Delay
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