XRD98L63 Datasheet, PDF (11/41 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L63
Wait A, Wait B and OB Lines Registers
WaitA
default
WaitB
default
OB Lines
default
D9
WL[11]
0
0
0
D8
WL[10]
0
0
0
D7
WL[9]
0
0
OBL[7]
1
D6
WL[8]
0
0
OBL[6]
0
D5
WL[7]
0
0
OBL[5]
0
D4
WL[6]
0
0
OBL[4]
0
D3
WL[5]
0
0
OBL[3]
0
D2
WL[4]
0
0
OBL[2]
0
D1
WL[3]
0
WL[1]
0
OBL[1]
1
D0
WL[2]
0
WL[0]
1
OBL[0]
0
WL[11:0] and OBL[7:0] are used by the Black Level Calibration logic in the Frame mode to determine which
lines to use for Calibration. (Frame mode is not currently supported)
See the “Black Level Offset Calibration” section (pg. 19) for more information.
CDAC Even and CDAC Odd Registers
CDAC Even
default
CDAC Odd
default
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CDE[8] CDE[7] CDE[6] CDE[5] CDE[4] CDE[3] CDE[2] CDE[1] CDE[0]
0
0
0
0
0
0
0
0
0
0
CDO[8] CDO[7] CDO[6] CDO[5] CDO[4] CDO[3] CDO[2] CDO[1] CDO[0]
0
0
0
0
0
0
0
0
0
0
CDE[8:0] and CDO[8:0] are used to program the internal Coarse Offset DAC in the Manual Calibration
mode. In the normal, single gain mode the value in CDE[8:0] is used. In the Multiple Gain mode, CDE[8:0] is
used for Even lines and CDO[8:0] is used for Odd lines.
See the “Black Level Offset Calibration” section (pg. 19) for more information.
FDAC Even and FDAC Odd Registers
FDAC Even
default
FDAC Odd
default
D9
FDE[9]
0
FDO[9]
0
D8
FDE[8]
0
FDO[8]
0
D7
FDE[7]
0
FDO[7]
0
D6
FDE[6]
0
FDO[6]
0
D5
FDE[5]
0
FDO[5]
0
D4
FDE[4]
0
FDO[4]
0
D3
FDE[3]
0
FDO[3]
0
D2
FDE[2]
0
FDO[2]
0
D1
FDE[1]
0
FDO[1]
0
D0
FDE[0]
0
FDO[0]
0
FDE[9:0] and FDO[9:0] are used to program the internal Fine Offset DAC in the Manual Calibration mode. In
the normal, single gain mode the value in FDE[9:0] is used. In the Multiple Gain mode, FDE[9:0] is used for
Even lines and FDO[9:0] is used for Odd lines.
See the “Black Level Offset Calibration” section (pg. 19) for more information.
Control Register
Control
default
D9
ADCpd
0
D8
AFEpd
0
D7
CHIPpd
0
D6
D5
D4
D3
D2
D1
D0
OE MultGain MGsel[1] MGsel[0] MGstart MinClip OneV
1
0
0
0
0
1
0
The Control register is used to program various options.
ADCpd, power down the ADC block. 0=normal operation. 1=ADC power down.
AFEpd, power down the AFE block. 0=normal operation. 1=AFE power down.
OE, output enable control. 0=DB[11:0] in high Z mode. 1=DB[11:0] in active drive mode.
MultGain, enable the Multiple Gain mode. 0=single gain mode. 1= Multiple Gain mode.
MGsel[1:0], Multiple Gain timing mode select.
MGstart, Even or Odd starting condition for MGsel[1:0]=11. 0=start with Even line, 1=start with Odd line.
MinClip, minimum clip option. 0=minimum clip disabled, 1=minimum clip enabled.
OneV, 1 volt input range option. 0=0.8V maximum input range. 1=1.0V maximum input range.
See the “Chip Power Down” section (pg. 34) for information about ADCpd, AFEpd, CHIPpd and OE.
See the “Multiple Gain Mode” section (pg. 30) for information about MultGain, MGsel[1:0] and MGstart.
See the “Other Chip Controls and Features” section (pg. 34) for information about MinClip.
See the “One Volt Input Option” section (pg. 16) for information about OneV.
Rev.1.01
11