XRD98L63 Datasheet, PDF (15/41 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L63
ANALOG FRONT END (AFE)
Correlated Double Sample/Hold (CDS)
The function of the CDS block is to sense the voltage
difference between the black level and video level for
each pixel. The PGA amplifies the difference to the
desired level for the ADC. The CDS and PGA are fully
differential. The CCDIN pin should be connected, via a
capacitor, to the CCD output signal. The REFIN pin
should be connected, via a capacitor, to the CCD
“Common” voltage (typically the CCD ground is used as
the “Common” voltage). These capacitors, C1 and C2,
are typically 0.01µF ± 10% or better matching.
The internal timing signals φ1, φ2, and φ3, which are
generated from SBLK and SPIX, control the sampling
switches shown in Fig. 6. φ3 (reset reject switches) are
closed to simplify the operation described below.
At the beginning (or end) of every video line, the DC
restore switch forces one side of the external capaci-
tors to an internal bias level (Vbias1=1.2V). The DC
restore switch is controlled by the combination of the
CLAMP input signal ANDed with the φ2 clock.
The CLAMPopt bit in the Clock register controls the
circuit which generates the Vbias1 level. When
CLAMPopt=0 (the default condition), the Vbias1 level is
only generated while CLAMP is active. When CLAMP
is not active, the Vbias1 circuit is put in a stand-by
mode, reducing the supply current by about 1 mA.
When CLAMPopt=1, the Vbias1 circuit always runs at
full power.
During the black reference phase of each CCD pixel, the
φ1 (Sample Black Reference) switches are turned on,
shorting the CDSamp inputs to a second bias level
(Vbias2). The Coarse Offset DAC adds an adjustment
to the bias level (Vbias2) to cancel black level offset in
the CCD signal. When the φ1 switches turn off, the pixel
black reference level is held on the internal black
sample capacitors, and the CDSamp is ready to gain up
the CCD video signal.
During the video phase of each CCD pixel, the differ-
ence between the pixel black level and video level is
transmitted through the internal black sample capaci-
tors and converted to a fully differential signal by the
CDSamp. At this time, the φ2 (Sample Pixel value)
switches turn on, and the internal video sample capaci-
tors track the amplified difference. The Fine Offset DAC
adds offset adjustment to the PGA2 output (post gain).
Vbias2
External
DC blocking
capacitors
CCD
CCDin
C1
R E F in
CDS
φ1
φ3
Coarse
Offset
φ2
DAC
Internal
CDS
black sample
capacitors
amp
C2
CLAMP
φ2
Internal
video sam p le
capacitors
DC restore switches
Vbias1=1.2V
PGA
internal
ADC Clock
Fine
Offset
DAC
PGA1
PGA2
Rev.1.01
Figure 6. CDS and PGA Block Diagram
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