XRD98L63 Datasheet, PDF (34/41 Pages) Exar Corporation – CCD Image Digitizers with CDS, PGA and 12-Bit A/D

XRD98L63
OTHER CHIP CONTROLS & FEATURES
Chip Power Down
The Power Down mode can be activated by forcing the
PD pin high, or by writing a “1” to the CHIPpd bit in the
Control register. For normal operation, the PD pin must
be low and the CHIPpd bit must be “0”. In the Power
Down mode, all analog circuits are turned off, and the
output bus, DB[11:0], is put in the high impedance
mode. All the digital registers retain their values, so the
PGA gain, offset, and calibration will return to their
previous states. The serial interface pins remain active
in the Power Down mode. The PD pin and the CHIPpd
bit do not reset any internal registers.
In addition to the CHIPpd bit, there are two other power
down bits which only turn off portions of the chip.
AFEpd controls the CDS & PGA circuits. ADCpd
controls the ADC. AFEpd & ADCpd are included for
factory test and characterization purposes, they are not
intended for use in digital camera applications.
Digital Output Enable Control
The ADC digital output bus, DB[11:0], has 3-state
capability. When the OE bit in the control register is
high, and the OE Pin (pin 42) is low, the digital output
drivers are enabled and active. When the OE bit is low,
or the OE pin is high, the digital output drivers are
disabled and the bus is in the high impedance state.
The OE bit and OE pin only control the digital output
drivers, all other circuits on the chip will remain active.
The black level calibration can still run properly when
the outputs are in the high impedance state.
Chip Reset
The chip includes a Power-On-Reset function (POR),
so when the power supplies are turned on, the chip will
always power up with default values in all registers.
There are two methods to force a chip reset. The first
is to write a “1” to the RESET bit in the reset register.
This will reset the chip, and after a delay of about 10 ns,
the reset bit will automatically clear itself. The second
reset method is to force the RESET pin (pin # 43) low.
This will reset the chip until the RESET pin goes high
again. The RESET pin has an internal pull up.
Minimum Clip
The Minimum Clip feature helps reduce noise in black
areas of a digitized image by clipping ADC output data,
such that the minimum code out is the code pro-
grammed in to the Offset register, OB[7:0].
When MinClip=1 (the default condition), the digital
output data will be clipped such that:
DB[11:0] ≥ OB[7:0]
This feature does not clip the data used by the internal
Black level Calibration Logic.
Digital Output Clamp
The PBLK (Pre-Blanking) clock is used to disconnect
the CDS inputs from the CCD signal during vertical shift
time. When DOclamp=1 (the default condition), PBLK
is also used to force the digital output data to the code
stored in the Offset register, OB[7:0].
If (DOclamp=1) AND (PBLK=active)
THEN DB[11:0] = OB[7:0]
Setting Power and Performance with Rext
The power and performance levels of the
XRD98L63 are set by the value of Rext. Rext sets
the current bias level for the entire chip. Rext is
connected between pin 37 (BiasRes) and analog
ground (see Figure 29). This resistor should be
placed as close as possible to the pin and routed
directly to a ground plane in a PCB layout. A
surface mount carbon resistor is recommended.
Increasing the value of Rext will decrease the
power, linearity and noise performance of the
XRD98L63. Reducing the value of Rext will
improve the linearity and noise performance while
increasing power. The tested default value for
Rext is 18.2KΩ.
In order to match system to system performance
and set consistent manufacturable performance
levels between cameras, it is recommended that
the Rext resistor have <1% tolerance.
Rev.1.01
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