XR17L152 Datasheet, PDF (41/55 Pages) Exar Corporation – 3.3V PCI BUS DUAL UART

XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
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FCTR [3:0] - Auto RTS/DTR Flow Control Hysteresis Select
These bits select the auto RTS/DTR flow control hysteresis and only valid when TX and RX Trigger Table-D is
selected (FCTR bit-6 and 7 are set to logic 1). The RTS/DTR hysteresis is referenced to the RX FIFO trigger
level. After reset, these bits are set to logic 0 selecting the next FIFO trigger level for hardware flow control.
Table 16 below shows the 16 selectable hysteresis levels.
TABLE 16: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED
FCTR BIT-3 FCTR BIT-2 FCTR BIT-1 FCTR BIT-0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
RTS/DTR HYSTERESIS
(CHARACTERS)
0
+/- 4
+/- 6
+/- 8
+/- 8
+/- 16
+/- 24
+/- 32
+/- 12
+/- 20
+/- 28
+/- 36
+/- 40
+/- 44
+/- 48
+/- 52
FCTR[4]: Infrared RX Input Logic Select
• Logic 0 = Select RX input as active high encoded IrDA data, normal, (default).
• Logic 1 = Select RX input as active low encoded IrDA data, inverted.
FCTR[5]: Auto RS485 Enable
This bit overrides the EN485# pin selection.
Auto RS485 half duplex control enable/disable.
• Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
• Logic 1 = Enable Auto RS485 half duplex direction control. RTS# output changes its logic level from 1 to 0
when finished sending the last stop bit of the last character out of the TSR register. It changes back to logic
level 1 from 0 when a data byte is loaded into the THR or transmit FIFO. The change to logic 1 occurs prior
sending the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register
(TSR) empty.
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