XR17L152 Datasheet, PDF (27/55 Pages) Exar Corporation – 3.3V PCI BUS DUAL UART

XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
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TABLE 11: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS
A3-A0
REG
NAME
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0 COMMENT
0 0 0 0 RHR
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0 LCR[7]=0
0 0 0 0 THR
W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0 LCR[7]=0
0000
DLL
R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0 LCR[7]=1
0 0 0 1 DLM R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0 LCR[7]=1
0001
IER
R/W
0/
0/
0/
0
Modem RX Line TX Empty RX Data
CTS/
RTS/ Xon/Xoff/
DSR# Int. DTR# Int. Sp. Char.
Status Int. Status Int. Int.
Enable Enable Enable
Int.
Enable
Enable Enable
Int.
Enable
0010
ISR
R
FIFOs FIFOs
0/
0/
INT
INT
INT
INT
Enable
Enable
Delta-
Xoff/spe-
Flow Cntl cial char
Source
Bit-3
Source
Bit-2
Source
Bit-1
Source
Bit-0
0 0 1 0 FCR
W RX FIFO RX FIFO
0/
0/
DMA TX FIFO RX FIFO FIFOs
Trigger Trigger
TX FIFO TX FIFO
Mode
Reset
Reset Enable
Trigger Trigger
0011
LCR
R/W Divisor Set TX Set Parity Even Par- Parity Stop Bits Word
Word
Enable Break
ity
Enable
Length Length
Bit-1
Bit-0
0100
MCR
R/W
0/
0/
0/
Internal
Lopback
BRG
IR
XonAny Enable
Prescaler _Enable
(OP2)¹
(OP1)¹
RTS/DTR
Flow Sel
RTS# Pin
Control
DTR# Pin
Control
0101
0110
LSR
MSR
R/W
R
RX FIFO
ERROR
CD
TSR
Empty
RI
THR
Empty
DSR
RX Break RX Fram- RX Parity RX Over- RX Data
ing Error Error
run
Ready
CTS
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
MSR
W
RS485 RS485 RS485 RS485 DLY- Reserved Reserved Reserved Reserved
DLY-3
DLY-2
DLY-1
0
0 1 1 1 SPR R/W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0 User Data
1 0 0 0 FCTR R/W
TRG
Table
Bit-1
TRG
Table
Bit-0
Auto
RS485
Enable
Invert IR RTS/DTR RTS/DTR RTS/DTR RTS/DTR
RX Input Hyst Bit-3 Hyst Bit-2 Hyst Bit-1 Hyst Bit-0
1001
EFR
R/W Auto CTS/ Auto RTS/ Special Enable Software Software Software Software
DSR
Enable
DTR
Enable
Char
Select
IER [7:5], ^{Flow Cntl Flow Cntl Flow Cntl Flow Cntl}
ISR [5:4], Bit-3
Bit-2
Bit-1
Bit-0
FCR[5:4],
MCR[7:5,2]
MSR[7:4]
1 0 1 0 TXCNT R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1 0 TXTRG W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1 1 RXCNT R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
1 0 1 1 RXTRG W
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
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