XR17L152 Datasheet, PDF (15/55 Pages) Exar Corporation – 3.3V PCI BUS DUAL UART

XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
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DISCONTINUED
1.2.6 SLEEP [31:24] - (default 0x00)
The first two bits of the Sleep register enables each UART channel separately to enter Sleep mode. The upper
bits 2 to 7 are reserved. Sleep mode reduces power consumption when the system needs to put the UART(s)
to idle. The UART enters Sleep mode when there is no interrupt pending. When both UARTs are put to sleep,
the on-chip oscillator shuts off to further conserve power. In this case, the XR17L152 is awakened on any of
the channels by a receive data byte or a change on the serial port. The UART is ready after 32 crystal clocks to
ensure full functionality. Also, a special interrupt is generated with an indication of no pending interrupt. Logic 0
(default) disables sleep mode and logic 1 enables it.
SLEEP Register
Individual UART Channel Sleep Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Ch-1 Ch-0
1.2.7 Device Identification and Revision
There are 2 internal registers that provide device identification and revision, DVID and DREV registers. The 8-
bit content in the DVID register provides device identification. A return value of 0x22 from this register indicates
the device is an XR17C152 or an XR17L152. The DREV register returns an 8-bit value of 0x01 for revision A
with 0x02 equals to revision B and so forth. This information is very useful to the software driver for identifying
which device it is communicating with and to keep up with revision changes.
DVID [15:8]
Device identification for the type of UART. The upper nibble indicates it is an XR17Cxxx or XR17Lxxx series
device with lower nibble indicating the number of channels.
Examples:
XR17C158 = 0x28
XR17C154 or XR17L154 = 0x24
XR17C152 or XR17L152 = 0x22
DREV [7:0]
Revision number of the XR17L152. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth.
REGB [23:16] (default 0x00)
REGB register provides a control for simultaneous write to both UARTs configuration register or individually.
This is very useful for device initialization in the power up and reset routines. Also, the register provides a
facility to interface to the non-volatile memory device such as a 93C46 EEPROM. In embedded applications,
the user can use this facility to store proprietary data.
1.2.8 REGB Register
REGB[16] (Read/Write) Logic 0 (default) write to each UART configuration registers individually.
Logic 1 enables simultaneous write to both UARTs configuration register.
REGB[19:17]
Reserved.
REGB[20] (Write-Only)
Control the EECK, clock, output (pin 116) on the EEPROM interface.
REGB[21] (Write-Only)
Control the EECS, chips select, output (pin 115) to the EEPROM device.
REGB[22] (Write-Only)
EEDI (pin 114) data input. Write data to the EEPROM device.
REGB[23] (Read-Only)
EEDO (pin 113) data output. Read data from the EEPROM device.
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