XR17L152 Datasheet, PDF (22/55 Pages) Exar Corporation – 3.3V PCI BUS DUAL UART

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XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
TABLE 9: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
OUTPUT Data Rate OUTPUT Data Rate DIVISOR FOR 16x DIVISOR FOR 16x DLM PROGRAM DLL PROGRAM D^ATA R^ATE
MCR Bit-7=1
MCR Bit-7=0 Clock (Decimal) Clock (HEX) VALUE (HEX) VALUE (HEX) ERROR (%)
100
400
2304
900
09
00
0
600
2400
384
180
01
80
0
1200
4800
192
C0
00
C0
0
2400
9600
96
60
00
60
0
4800
19.2k
48
30
00
30
0
9600
38.4k
24
18
00
18
0
19.2k
76.8k
12
0C
00
0C
0
38.4k
153.6k
6
06
00
06
0
57.6k
230.4k
4
04
00
04
0
115.2k
460.8k
2
02
00
02
0
230.4k
921.6k
1
01
00
01
0
4.2 Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation
Automatic RTS/DTR and CTS/DSR flow control, also known as hardware flow control, is used to prevent data
overrun to the local receiver FIFO and remote receiver FIFO. The RTS#/DTR# output pin is used to request
remote unit to suspend/restart data transmission while the CTS#/DSR# input pin is monitored to suspend/
restart local transmitter. The auto RTS/DTR and auto CTS/DSR flow control features are individually selected
to fit specific application requirement and enabled through EFR bit-6 and 7 and MCR bit-2 for either RTS/CTS
or DTR/DSR control signals. The auto RTS/DTR function must be started by asserting RTS/DTR# output pin
(MCR bit-0 or 1 to logic 1) after it is enabled. Figure 9 below explains how it works.
Two interrupts associated with RTS/DTR and CTS/DSR flow control have been added to give indication when
RTS/DTR# pin or CTS/DSR# pin is de-asserted during operation. The RTS/DTR and CTS/DSR interrupts must
be first enabled by EFR bit-4, and then enabled individually by IER bit-6 and 7, and chosen with MCR bit-2.
Automatic hardware flow control is selected by setting bits 6 (RTS) and 7 (CTS) of the EFR register to logic 1.
If CTS# pin transitions from logic 0 to logic 1 indicting a flow control request, ISR bit-5 will be set to logic 1, (if
enabled via IER bit 6-7), and the UART will suspend TX transmissions as soon as the stop bit of the character
in process is shifted out. Transmission is resumed after the CTS# input returns to logic 0, indicating more data
may be sent.
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