XR17L152 Datasheet, PDF (34/55 Pages) Exar Corporation – 3.3V PCI BUS DUAL UART

áç
DISCONTINUED
XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a logic 1.
• Logic 0 = No transmit FIFO reset (default).
• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
This bit is only active when FCR bit-0 is a logic 1.
This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy
software.
• Logic 0 = Set DMA to mode 0 (default).
• Logic 1 = Set DMA to mode 1.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
The FCTR Bits 6-7 are associated with these 2 bits by selecting one of the four tables. The 4 user selectable
trigger levels in 4 tables are supported for compatibility reasons. These 2 bits set the trigger level for the
transmit FIFO interrupt. The UART will issue a transmit interrupt when the number of characters in the FIFO
falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the
trigger level on last re-load. Table 13 below shows the selections. Note that the receiver and the transmitter
cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 6-7 are associated with these 2 bits. These 2 bits are used to set the trigger level for the
receiver FIFO interrupt. Table 13 shows the complete selections. Note that the receiver and the transmitter
cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side.
34