XR17L152 Datasheet, PDF (13/55 Pages) Exar Corporation – 3.3V PCI BUS DUAL UART

XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
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DISCONTINUED
TABLE 6: UART CHANNEL [1:0] INTERRUPT CLEARING:
RXRDY is cleared by reading data in the RX FIFO until it falls below the trigger level.
RXRDY Time-out interrupt is cleared when the RX FIFO becomes empty.
RX Line Status interrupt clears after reading the LSR register.
TXRDY interrupt clears after reading ISR register.
Modem Status Register interrupt clears after reading MSR register.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register.
Xoff/Xon delta and special character detect interrupt clears after reading the ISR register.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
1.2.2 General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT
0XXX-XX-00-00)
A 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal
crystal oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a one-time event or
re-triggerable for a continuous interval. An interrupt may be generated in the INT Register when the timer times
out. It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. These
registers provide start/stop and re-triggerable or one-shot operation. The time-out output of the Timer can be
set to generate an interrupt for system or event alarm.
FIGURE 5. TIMER/COUNTER CIRCUIT.
TIM ERM SB and TIM ERLSB
(16-bit Value)
TMRCK
1
OSC. CLOCK
0
1 6 -B it
Tim e-out
1
Tim er/C ounter
0
C lo ck
T IM E R C N T L [3] ^Select
S ta rt/S to p
TIM ERCNTL [1]
T IM E R C N T L [2 ] ^{Single/R e-triggerable}
R e-trigg er
0
1
S in g le -s h o t
T IM E R C N T L [0] ^{Tim er Interrupt Enable}
TIM ERCNTL [4]
Tim er Interrupt, C h-0 IN T=7
N o Interrupt
1
M PIO [0]
0
M PIO LVL[0]
TABLE 7: TIMER CONTROL REGISTERS
TIMERCNTL [0] Logic zero (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
TIMERCNLT [1] Logic zero (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
TIMERCNTL [2] Logic zero (default) selects re-trigger timer function and logic one selects one-shot (timer function.
TIMERCNTL [3] Logic zero (default) selects internal and logic one selects external clock to the timer/counter.
TIMERCNTL [4] Routes the Timer-Counter interrupt to MPIO[0] if MPIOSEL[0]=0 for external event control.
TIMERCNTL [7:5] Reserved (defaults to zero).
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