W78E054D Datasheet, PDF (9/89 Pages) List of Unclassifed Manufacturers – 8-bit microcontroller

W78E054D/W78E052D Data Sheet
5 PIN DESCRIPTIONS
SYMBOL
EA
TYPE DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address
I _{and data will not be present on the bus if EA pin is high and the program coun-}
ter is within internal ROM area. Otherwise they will be present on the bus.
PSEN
ALE
RST
XTAL1
XTAL2
VSS
VDD
P0.0P0.7
P1.0P1.7
P2.0P2.7
PROGRAM STORE ENABLE: ^PSEN enables the external ROM data onto the
O H Port 0 address/data bus during fetch and MOVC operations. When internal ROM
access is performed, no ^PSEN strobe signal outputs from this pin.
OH
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that sepa-
rates the address from the data on Port 0.
IL
RESET: A high on this pin for two machine cycles while the oscillator is running
resets the device.
I
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an ex-
ternal clock.
O CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
I GROUND: Ground potential
I POWER SUPPLY: Supply voltage for operation.
I/O D
PORT 0: Port 0 is an open-drain bi-directional I/O port. This port also provides a
multiplexed low order address/data bus during accesses to external memory.
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
I/O H _{T2 (P1.0): Timer/Counter 2 external count input}
T2EX (P1.1): Timer/Counter 2 Reload/Capture control
I/O H
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups.
provides the upper address bits for accesses to external memory.
This
port
also
Publication Release Date: Jun 9, 2015
-9-
Revision A13