W78E054D Datasheet, PDF (71/89 Pages) List of Unclassifed Manufacturers – 8-bit microcontroller

W78E054D/W78E052D Data Sheet
20.3.2 Program Fetch Cycle
PARAMETER
Address Valid to ALE Low
Address Hold from ALE Low
ALE Low to ^PSEN Low
PSEN Low to Data Valid
Data Hold after PSEN High
Data Float after PSEN High
ALE Pulse Width
PSEN Pulse Width
SYMBOL
Taas
Taah
Tapl
Tpda
Tpdh
Tpdz
Talw
Tpsw
MIN.
1 TCP -

1 TCP -

1 TCP -

-
0
0
2 TCP -

3 TCP -

TYP.
-
-
-
-
-
-
2 TCP
3 TCP
MAX.
-
-
-
2 TCP
1 TCP
1 TCP
-
-
Notes:
1. P0.0P0.7, P2.0P2.7 remains stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "" (due to buffer driving delay and wire loading) is 20 nS.
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
NOTES
4
1, 4
4
2
3
4
4
20.3.3 Data Read Cycle
PARAMETER
SYMBOL MIN.
TYP.
ALE Low to RD Low
RD Low to Data Valid
Tdar
Tdda
3 TCP - -
-
-
Data Hold from RD High
Tddh
0
-
Data Float from RD High
Tddz
0
-
RD Pulse Width
Tdrd
6 TCP - 6 TCP
Notes:
1. Data memory access time is 8 TCP.
2. "" (due to buffer driving delay and wire loading) is 20 nS.
MAX.
3 TCP +
4 TCP
2 TCP
2 TCP
-
UNIT
nS
nS
nS
nS
nS
NOTES
1, 2
1
2
20.3.4 Data Write Cycle
PARAMETER
ALE Low to ^WR Low
Data Valid to ^WR Low
SYMBOL
Tdaw
Tdad
MIN.
TYP.
3 TCP - -
1 TCP - -
MAX.
3 TCP +
-
UNIT
nS
nS
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Publication Release Date: Jun 9, 2015
Revision A13