W78E054D Datasheet, PDF (54/89 Pages) List of Unclassifed Manufacturers – 8-bit microcontroller

W78E054D/W78E052D Data Sheet
15 WATCHDOG TIMER
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a sys-
tem monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electro-
magnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values de-
pending on the clock speed. The Watchdog timer will de disabled on reset. In general, software should
restart the Watchdog timer to put it into a known state. The control bits that support the Watchdog tim-
er are discussed below.
ENW : Enable watchdog if set.
CLRW : Clear watchdog timer and Pre-scalar if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watchdog is disabled un-
der IDLE mode. Default is cleared.
PS2, PS1, PS0: Watchdog Pre-scalar timer select. Pre-scalar is selected when set PS20 as follows:
PS2 PS1 PS0
Pre-scalar select
00 0
2
00 1
8
01 0
4
01 1
16
10 0
32
10 1
64
11 0
128
11 1
256
The time-out period is obtained using the following equation for 12T per machine cycle:
1 _{ 214  Pr e  scalar 1000 12ms}
OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, Pre-scalar and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
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Publication Release Date: Jun 9, 2015
Revision A13