W78E054D Datasheet, PDF (45/89 Pages) List of Unclassifed Manufacturers – 8-bit microcontroller

W78E054D/W78E052D Data Sheet
13 INTERRUPTS
The W78E054D/W78E052D has a 4 priority level interrupt structure with 8 interrupt sources. Each of
the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the
interrupts can be globally enabled or disabled.
13.1 Interrupt Sources
The External Interrupts ^INT0 and ^INT1 can be either edge triggered or level triggered, depending on
bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to gener-
ate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine cycle. If
the sample is high in one cycle and low in the next, then a high to low transition is detected and the
interrupts request flag IEx in TCON o is set. The flag bit requests the interrupt. Since the external in-
terrupts are sampled every machine cycle, they have to be held high or low for at least one complete
machine cycle. The IEx flag is automatically cleared when the service routine is called. If the level trig-
gered mode is selected, then the requesting source has to hold the pin low till the interrupt is serviced.
The IEx flag will not be cleared by the hardware on entering the service routine. If the interrupt contin-
ues to be held low even after the service routine is completed, then the processor may acknowledge
another interrupt request from the same source. Note that the external interrupts ^INT2 and ^INT3 . By
default, the individual interrupt flag corresponding to external interrupt 2 to 3 must be cleared manually
by software.
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the over-
flow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware
when the timer interrupt is serviced. The Timer 2 interrupt is generated by a logical OR of the TF2 and
the EXF2 flags. These flags are set by overflow or capture/reload events in the timer 2 operation. The
hardware does not clear these flags when a timer 2 interrupt is executed. Software has to resolve the
cause of the interrupt between TF2 and EXF2 and clear the appropriate flag.
The Serial block can generate interrupts on reception or transmission. There are two interrupt sources
from the Serial block, which are obtained by the RI and TI bits in the SCON SFR, These bits are not
automatically cleared by the hardware, and the user will have to clear these bits using software.
All the bits that generate interrupts can be set or reset by hardware, and thereby software initiated in-
terrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or
clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to disa-
ble all the interrupts, at once.
Source
External Interrupt 0
External Interrupt 1
Serial Port
External Interrupt 2
Vector Address
0003h
0013h
0023h
0033h
Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 Overflow
External Interrupt 3
Vector Address
000Bh
001Bh
002Bh
003Bh
Table 13–1 W78E054D/W78E052D interrupt vector table
13.2 Priority Level Structure
There are 4 priority levels for the interrupts high, low. Naturally, a higher priority interrupt cannot be
interrupted by a lower priority interrupt. However there exists a pre-defined hierarchy amongst the in-
terrupts themselves. This hierarchy comes into play when the interrupt controller has to resolve simul-
taneous requests having the same priority level. This hierarchy is defined as shown on Table.
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Publication Release Date: Jun 9, 2015
Revision A13