W78E054D Datasheet, PDF (47/89 Pages) List of Unclassifed Manufacturers – 8-bit microcontroller

W78E054D/W78E052D Data Sheet
Each interrupt source can be individually programmed to one of 2 priority levels by setting or clearing
bits in the IP registers. An interrupt service routine in progress can be interrupted by a higher priority
interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. So, if two requests of different priority levels are
received simultaneously, the request of higher priority level is serviced.
If requests of the same priority level are received simultaneously, an internal polling sequence deter-
mines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking
is only used to resolve simultaneous requests of the same priority level.
Table below summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits,
arbitration ranking, and External interrupt may wake up the CPU from Power Down mode.
Source
Flag Vector
address
External Interrupt 0 IE0 0003H
Timer 0 Overflow TF0 000BH
External Interrupt 1 IE1 0013H
Timer 1 Overflow TF1 001BH
Serial Port
RI + 0023H
TI
Timer 2 Over-
flow/Match
TF2 002BH
External Interrupt 2 IE2 0033H
External Interrupt 3 IE3 003BH
Enable bit Interrupt
Priority
Flag cleared Arbitration
by
ranking
EX0 (IE.0)
ET0 (IE.1)
EX1 (IE.2)
ET1 (IE.3)
ES (IE.4)
IPH.0, IP.0 Hardware,
software
IPH.1, IP.1 Hardware,
software
IPH.2, IP.2 Hardware,
software
IPH.3, IP.3 Hardware,
software
IPH.4, IP.4 Software
1(highest)
2
3
4
5
ET2 (IE.5) IPH.5, IP.5 Software
6
EX2
(XICON.2)
EX3
(XICON.6)
IPH.6,
PX2
IPH.7,
PX3
Hardware,
software
Hardware,
software
7
8(lowest)
Power-
down
wakeup
Yes
No
Yes
No
No
No
Yes
Yes
Table 13–2 Summary of interrupt sources
13.3 Interrupt Response Time
The response time for each interrupt source depends on several factors, such as the nature of the in-
terrupt and the instruction underway. In the case of external interrupts INT0 and INT1, they are sam-
pled at S5P2 of every machine cycle and then their corresponding interrupt flags IEx will be set or re-
set. The Timer 0 and 1 overflow flags are set at C3 of the machine cycle in which overflow has oc-
curred. These flag values are polled only in the next machine cycle. If a request is active and all three
conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes four ma-
chine cycles to be completed. Thus there is a minimum time of five machine cycles between the inter-
rupt flag being set and the interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or
equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the
service routine currently being executed. If the polling cycle is not the last machine cycle of the instruc-
tion being executed, then an additional delay is introduced. The maximum response time (if no other
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Publication Release Date: Jun 9, 2015
Revision A13