W78E054D Datasheet, PDF (24/89 Pages) List of Unclassifed Manufacturers – 8-bit microcontroller

W78E054D/W78E052D Data Sheet
6 CLRW
5 WIDL
2-0 PS2-0
Clear watch-dog timer and Pre-scalar if set. This flag will be cleared automatical-
ly.
If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is
disabled under IDLE mode. Default is cleared.
Watch-dog Pre-scalar timer select. Pre-scalar is selected when set PS20 as fol-
lows:
PS2 PS1 PS0
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
PRE-SCALAR SELECT
2
8
4
16
32
64
128
256
Port 1
Bit: 7
P1.7
Mnemonic: P1
BIT NAME
7-0 P1.[7:0]
6
5
4
3
2
1
0
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Address: 90h
FUNCTION
General purpose I/O port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is
read.
Serial Port Control
Bit: 7
6
5
4
3
2
1
0
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
Mnemonic: SCON
Address: 98h
BIT NAME
FUNCTION
7 SM0/FE Serial port mode select bit 0 or Framing Error Flag: The SMOD0 bit in PCON
SFR determines whether this bit acts as SM0 or as FE. The operation of SM0 is
described below. When used as FE, this bit will be set to indicate an invalid stop
bit. This bit must be manually cleared in software to clear the FE condition.
6 SM1
Serial Port mode select bit 1. See table below.
5 SM2
Multiple processors communication. Setting this bit to 1 enables the multiproces-
sor communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1,
then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if
SM2 = 1, then RI will not be activated if a valid stop bit was not received. In
mode 0, the SM2 bit controls the serial port clock. If set to 0, then the serial port
runs at a divide by 12 clock of the oscillator. This gives compatibility with the
standard 8052. When set to 1, the serial clock become divide by 4 of the oscilla-
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Publication Release Date: Jun 9, 2015
Revision A13