NUC950ADN Datasheet, PDF (61/629 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC950ADN
32-BIT ARM926EJ-S BASED MCU
Clock Divider Control Register (CLKDIV)
Register
Address
R/W
Description
Reset Value
CLKDIV _{0xB000_0208}
R/W
Clock Divider Control Register
0x0400_0000
31
RESERVED
23
15
7
30
29
28
G2DDIV
RESERVED
22
21
20
RESERVED
14
13
12
VCKDIV
6
5
4
RESERVED
27
26
25
24
APBCKDIV
AHBCKDIV
19
18
17
16
UART1DIV
11
10
9
8
ACKDIV
3
2
1
0
CPUCKDIV
Bits
Descriptions
[30]
G2DDIV
[29:28] RESERVED
G2D Clock Divider Control Register
0: divider 2
1: divider 1
AMBA APB Clock Divider Control Register
[27:26] APBCKDIV
APBCKDIV
0
0
0
1
1
0
1
1
Clock Frequency
Reserved
AHBCLK/2
AHBCLK/4
AHBCLK/8
AMBA AHB Clock (AHBCLK) Divider Control Register
[25:24] AHBCKDIV
AHBCKDIV
0
0
0
1
1
0
1
1
Clock Frequency
CPUCLK/1
CPUCLK/2
CPUCLK/4
CPUCLK/8
61
Publication Release Date: Jun. 18, 2010
Revision: A4