NUC950ADN Datasheet, PDF (217/629 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC950ADN
Bits
[6]
[5]
[4]
[3]
Descriptions
FPResum
OCCHG
OCACT
PENCHG
32-BIT ARM926EJ-S BASED MCU
Force Port Resume (R/W)
1= Resume detected/driven on port. 0=No resume (Kstate) detected/driven
on port. Default = 0. This functionality defined for manipulating this bit
depends on the value of the Suspend bit. For example, if the port is not
suspended (Suspend and Enabled bits are a one) and software transitions
this bit to a one, then the effects on the bus are undefined.
Software sets this bit to a 1 to drive resume signaling. The Host Controller
sets this bit to a 1 if a J-to-K transition is detected while the port is in the
Suspend state. When this bit transitions to a one because a J-to-K transition
is detected, the Port Change Detect bit in the USBSTS register is also set to a
one. If software sets this bit to a one, the host controller must not set the
Port Change Detect bit.
Note that when the EHCI controller owns the port, the resume sequence
follows the defined sequence documented in the USB Specification Revision
2.0. The resume signaling (Full-speed 'K') is driven on the port as long as
this bit remains a one. Software must appropriately time the Resume and set
this bit to a zero when the appropriate amount of time has elapsed. Writing a
zero (from one) causes the port to return to high-speed mode (forcing the
bus below the port into a high-speed idle). This bit will remain a one until the
port has switched to the high-speed idle. The host controller must complete
this transition within 2 milliseconds of software setting this bit to a zero.
This field is zero if Port Power is zero.
Over-current Change (R/WC)
Default = 0. 1=This bit gets set to a one when there is a change to Over-
current Active. Software clears this bit by writing a one to this bit position.
Over-current Active (RO)
Default = 0. 1=This port currently has an over current condition. 0=This port
does not have an over-current condition. This bit will automatically transition
from a one to a zero when the over current condition is removed.
Port Enable/Disable Change (R/WC)
1=Port enabled/disabled status has changed. 0=No change. Default = 0. For
the root hub, this bit gets set to a one only when a port is disabled due to the
appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB
Specification for the definition of a Port Error). Software clears this bit by
writing a 1 to it.
This field is zero if Port Power is zero.
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Publication Release Date: Jun. 18, 2010
Revision: A4