NUC950ADN Datasheet, PDF (172/629 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC950ADN
32-BIT ARM926EJ-S BASED MCU
Channel 0/1 Control Register (GDMA_CTL0, GDMA_CTL1)
Register
Address
R/W Description
Reset Value
GDMA_CTL0
GDMA_CTL1
0xB000_4000
0xB000_4020
R/W Channel 0 Control Register
R/W Channel 1 Control Register
0x0000_0000
0x0000_0000
The control registers has two formats for descriptor fetch and non-descriptor fetch function respectively. The
functionality of each control bit is described in following table.
1. Non-Descriptor fetches Mode
31
23
RESERVED
15
RESERVED
7
SAFIX
30
22
SABNDERR
14
RESERVED
6
DAFIX
29
28
RESERVED
21
20
DABNDERR RESERVED
13
12
TWS
5
4
SADIR
DADIR
27
19
AUTOIEN
11
26
25
RESERVED
18
17
RESERVED BLOCK
10
9
RESERVED
3
2
GDMAMS
1
BME
24
RESERVED
16
SOFTREQ
8
0
GDMAEN
2. Descriptor fetches Mode
31
30
29
28
27
26
25
24
RESERVED
RESERVED RESERVED
23
22
21
20
19
18
17
16
RESERVED SABNDERR DABNDERR
RESERVED
BLOCK SOFTREQ
15
14
13
12
11
10
9
8
RESERVED
TWS
RESERVED D_INTS
RESERVED
7
6
5
4
3
2
1
0
SAFIX
DAFIX
SADIR
DADIR
GDMAMS
BME
GDMAEN
NOTE:
 The bit [REQ_ATV] and [ACK_ATV] must be set first before using I/O to Memory mode with
Descriptor fetch transfer. These two bits cannot do any setup in command information within
descriptor list configuration. The [SABNDERR], [DABNDERR], [GDMAERR] can also be read at
descriptor fetch mode.
 Regardless of GDMA operate in descriptor mode or non-descriptor mode, when transfer width is 16-
bit (half word) and the address with decrement function enable for starting source address or
destination address or both are used should set the least two bit of addresses is 0xF.
172
Publication Release Date: Jun. 18, 2010
Revision: A4