NUC950ADN Datasheet, PDF (559/629 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC950ADN
32-BIT ARM926EJ-S BASED MCU
GPIO PortE Direction Control Register (GPIOE_DIR)
Register Address
GPIOE_DIR 0xB800_3024
R/W Description
R/W GPIO portE in/out direction control register
Reset Value
0x0000_0000
31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
15
14
13
12
11
10
9
8
RESERVED
OUTEN
7
6
5
4
3
2
1
0
OUTEN
Bits
[13:0]
Descriptions
OUTEN
GPIO PortE Output Enable Control
Each GPIO pin can be enabled individually by setting the corresponding control bit.
0 = Input Mode
1 = Output Mode
Bit12-bit8 and bit5-bit4 are no action
559
Publication Release Date: Jun. 18, 2010
Revision: A4