NUC950ADN Datasheet, PDF (568/629 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC950ADN
32-BIT ARM926EJ-S BASED MCU
GPIO PortH De-bounce Enable Control Register (GPIOH_DBNCE)
Register
GPIOH_DBNCE
Address
0xB800_3050
R/W
R/W
Description
GPIO PortH de-bounce control register
Reset Value
N/A
31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
15
14
13
12
11
10
9
8
RESERVED
DBCLKSEL
7
6
5
4
3
2
1
0
RESERVED
DBEN2
DBEN1
DBEN0
Bits
Descriptions
De-bounce Clock Selection
[10:8]
DBCLKSEL
These 3 bits are used to select the clock rate for de-bouncer circuit. The
relationship between the system clock HCLK and the de-bounce clock TCLK_BUN
is as follows:
TCLK_BUN = HCLK / 2^DBCLKSEL
De-bounce Circuit Enable for GPIOH2 (nIRQ2) Input
[2]
DBEN2
1 = Enable De-bounce
0 = Disable De-bounce
De-bounce Circuit Enable for GPIOH1 (nIRQ1) Input
[1]
DBEN1
1 = Enable De-bounce
0 = Disable De-bounce
De-bounce Circuit Enable for GPIOH0 (nIRQ0) Input
[0]
DBEN0
1 = Enable De-bounce
0 = Disable De-bounce
568
Publication Release Date: Jun. 18, 2010
Revision: A4