NUC950ADN Datasheet, PDF (286/629 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC950ADN
32-BIT ARM926EJ-S BASED MCU
DMA Control Status Register (DMA_CTRL_STS)
Register
Address
R/W Description
Default Value
DMA_CTRL_STS 0xB000_605C
R/W DMA Control Status Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
RST_DMA ^SCAT_GA_EN DMA_EN DMA_RD
DMA_ADDR
Bits
[7]
[6]
[5]
[4]
[3:0]
Descriptions
RST_DMA
SCAT_GA_EN
DMA_EN
DMA_RD
DMA_ADDR
Reset DMA state machine.
Scatter gather function enable
DMA Enable Bit
DMA Operation Bit.
If ‘1’, the operation is a DMA read and if ‘0’ the operation is a DMA
write.
DMA ep_addr Bits
When enable scatter gather DMA function, SCAT_GA_EN needs to be set high and DMA_CNT set to 8
bytes. Then DMA will enable to fetch the descriptor which describes the real memory address and length.
The descriptor will be a
8-byte format, like the following:
[31] [30]
EOT RD
[29:0]
MEM_ADDR[31:0]
reserved
count[19:0]
286
Publication Release Date: Jun. 18, 2010
Revision: A4