NUC950ADN Datasheet, PDF (520/629 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC950ADN
32-BIT ARM926EJ-S BASED MCU
Timer Control and Status Register 0~4 (TCR0~TCR4)
Register
TCSR0
TCSR1
TCSR2
TCSR3
TCSR4
Address R/W/C Description
0xB800_1000
0xB800_1004
0xB800_1020
0xB800_1024
0xB800_1040
R/W
R/W
R/W
R/W
R/W
Timer Control and Status Register 0
Timer Control and Status Register 1
Timer Control and Status Register 2
Timer Control and Status Register 3
Timer Control and Status Register 4
Reset Value
0x0000_0005
0x0000_0005
0x0000_0005
0x0000_0005
0x0000_0005
31
30
29
RESERVED
CE
IE
23
22
21
15
14
13
7
6
5
28
27
MODE
20
19
RESERVED
12
11
RESERVED
4
3
PRESCALE
26
CRST
18
10
2
25
CACT
17
24
RESERVED
16
9
8
1
0
Bits
[30]
[29]
Descriptions
Counter Enable
CE
0 = Stops counting
1 = Starts counting
Interrupt Enable
IE
0 = Disables timer interrupt
1 = Enables timer interrupt. If timer interrupt is enabled, the timer asserts its
interrupt signal when the associated counter decrements to zero.
520
Publication Release Date: Jun. 18, 2010
Revision: A4