NUC950ADN Datasheet, PDF (227/629 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC950ADN
32-BIT ARM926EJ-S BASED MCU
Host Controller Interrupt Status Register (HcIntSts)
Register
HcIntSts
Address
0xB000_700C
R/W
R/W
Description
Host Controller Interrupt Status Register
Reset Value
0x0000_0000
31
30
Reserved
OC
23
22
15
14
7
Reserved
6
RHSC
29
21
13
5
FNOF
28
27
26
Reserved
20
19
18
Reserved
12
11
Reserved
4
3
UnRecErr _Resume
10
2
SOF
25
24
17
16
9
8
1
WBDnHD
0
SchOR
Bits
[30]
[6]
[5]
[4]
[3]
[2]
[1]
Descriptions
OC
RHSC
FNOF
UnRecErr
Resume
SOF
WBDnHD
Ownership Change
This bit is set when the OwnershipChangeRequest bit of
HcCommandStatus is set.
Root Hub Status Change
This bit is set when the content of HcRhStatus or the content of any
HcRhPortStatus register has changed.
Frame Number Overflow
Set when bit 15 of FrameNumber changes value.
Unrecoverable Error
This event is not implemented and is hard-coded to ‘0.’ Writes are ignored.
Resume Detected
Set when Host Controller detects resume signaling on a downstream port.
Start Of Frame
Set when the Frame Management block signals a ‘Start of Frame’ event.
Write Back Done Head
Set after the Host Controller has written HcDoneHead to HccaDoneHead.
227
Publication Release Date: Jun. 18, 2010
Revision: A4