NUC950ADN Datasheet, PDF (173/629 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC950ADN
32-BIT ARM926EJ-S BASED MCU
Control Register of Non-Descriptor fetches Mode:
Bits
[22]
[21]
[19]
[17]
Descriptions
SABNDERR
DABNDERR
AUTOIEN
BLOCK
Source Address Boundary Alignment Error Flag
If TWS [13:12]=10, GDMA_SRCB [1:0] should be 00
If TWS [13:12]=01, GDMA_SRCB [0] should be 0
Except the SADIR function enabled.
The address boundary alignment should be depended on TWS [13:12].
0 = the GDMA_SRCB is on the boundary alignment.
1 = the GDMA_SRCB not on the boundary alignment
The SABNDERR register bits just can be read only.
Destination Address Boundary Alignment Error Flag
If TWS [13:12]=10, GDMA_DSTB [1:0] should be 00
If TWS [13:12]=01, GDMA_DSTB [0] should be 0
Except the SADIR function enabled.
The address boundary alignment should be depended on TWS [13:12].
0 = the GDMA_DSTB is on the boundary alignment.
1 = the GDMA_DSTB not on the boundary alignment
The DABNDERR register bits just can be read only.
Auto initialization Enable
0 = Disables auto initialization
1 = Enables auto initialization, the GDMA_CSRC0/1, GDMA_CDST0/1, and
GDMA_CTCNT0/1 registers are updated by the GDMA_SRC0/1,
GDMA_DST0/1, and GDMA_TCNT0/1 registers automatically when
transfer is complete.
GDMA will start another transfer when SOFTREQ set again.
Bus Lock
0 = Unlocks the bus during the period of transfer
1 = locks the bus during the period of transfer
173
Publication Release Date: Jun. 18, 2010
Revision: A4