LM3S316 Datasheet, PDF (60/421 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
6.1.2.5
6.1.2.6
Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL)
register (see page 76). The BORIOR bit in the PBORCTL register must be set for a brown-out to
trigger a reset. The brown-out reset sequence is as follows:
1. When V_DD drops below V_BTH, an internal BOR condition is set.
2. If the BORWT bit in the PBORCTL register is set, the BOR condition is resampled sometime
later (specified by BORTIM) to determine if the original condition was caused by noise. If the
BOR condition is not met the second time, then no action is taken.
3. If the BOR condition exists, an internal reset is asserted.
4. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
5. The internal BOR signal is released after 500 µs to prevent another BOR condition from being
set before software has a chance to investigate the original cause.
The internal Brown-Out Reset timing is shown in Figure 20-11 on page 412.
Software Reset
Each peripheral can be reset by software. There are three registers that control this function (see
the SRCRn registers, starting on page 78). If the bit position corresponding to a peripheral is set,
the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the
clock gating control for peripherals and on-chip functions (see “System Control” on page 63).
Writing a bit lane with a value of 1 initiates a reset of the corresponding unit. Note that all reset
signals for all clocks of the specified unit are asserted as a result of a software-initiated reset.
The entire system can be reset by software also. Setting the SYSRESETREQ bit in the Cortex-M3
Application Interrupt and Reset Control register resets the entire system including the core. The
software-initiated system reset sequence is as follows:
1. A software system reset in initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3
Application Interrupt and Reset Control register.
2. An internal reset is asserted.
3. The internal reset is released and the controller fetches and loads the initial stack pointer, the
initial program counter, and the first instruction designated by the program counter, and then
begins execution.
The software-initiated system reset timing is shown in Figure 20-12 on page 412.
Watchdog Timer Reset
The watchdog timer module's function is to prevent system hangs. The watchdog timer can be
configured to generate an interrupt to the controller on its first time-out, and to generate a reset
signal on its second time-out.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer
Load (WDTLOAD) register (see page 190), and the timer resumes counting down from that value.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the
reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The
watchdog timer reset sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
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April 27, 2007
Preliminary