LM3S316 Datasheet, PDF (285/421 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S316 Data Sheet
13.3
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
t_Setup =(2*t_SSIClk )
t_Hold=t_SSIClk
SSIClk
SSIFss
SSIRx
First RX data to be
sampled by SSI slave
Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x00000000.
b. For slave mode (output enabled), set the SSICR1 register to 0x00000004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
4. Write the SSICR0 register with the following configuration:
– Serial clock rate (SCR)
– Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
– The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
– The data size (DSS)
5. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
„ Master operation
„ Freescale SPI mode (SPO=1, SPH=1)
„ 1 Mbps bit rate
„ 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) ' 1x106 = 20x106 / (CPSDVSR * (1 +
SCR))
In this case, if CPSDVSR=2, SCR must be 9.
The configuration sequence would be as follows:
1. Ensure that the SSE bit in the SSICR1 register is disabled.
2. Write the SSICR1 register with a value of 0x00000000.
April 27, 2007
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Preliminary