LM3S316 Datasheet, PDF (338/421 Pages) List of Unclassifed Manufacturers – Microcontroller

Inter-Integrated Circuit (I2C) Interface
Register 11: I²C Slave Control/Status (I2CSCSR), offset 0x004
This register accesses one control bit when written, and two status bits when read.
The read-only Status register consists of three bits: the FBR bit, the RREQ bit, and the TREQ bit. The
First Byte Received (FBR) bit is set only after the Stellaris device detects its own slave
address and receives the first data byte from the I²C master. The Receive Request (RREQ) bit
indicates that the Stellaris I²C device has received a data byte from an I²C master. Read one data
byte from the I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request
(TREQ) bit indicates that the Stellaris I²C device is addressed as a Slave Transmitter. Write one
data byte into the I2C Slave Data (I2CSDR) register to clear the TREQ bit.
The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the
Stellaris I²C slave operation.
I2C Slave Status Register (I2CSCSR): Read
Offset 0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FBR TREQ RREQ
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I2C Slave Control Register (I2CSCSR): Write
Offset 0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DA
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
Name
Read-Only Status Register
31:3
reserved
2
FBR
Type
Reset Description
RO
0
Reserved bits return an indeterminate value, and should
never be changed.
RO
0
Indicates that the first byte following the slave’s own
address is received. This bit is only valid when the RREQ
bit is set, and is automatically cleared when data has been
read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
338
April 27, 2007
Preliminary