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SI8421AD Datasheet, PDF (6/37 Pages) List of Unclassifed Manufacturers – LOW-POWER, SINGLE AND DUAL-CHANNEL DIGITAL ISOLATORS
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Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA = –40 to 125 ºC)
Parameter
Symbol Test Condition
Min
Typ
Max Unit
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
Si8420Bx
VDD1
VDD2
Si8421Bx
—
2.1
3.1
mA
—
5.0
6.3
—
3.7
5.4
mA
—
9.8
12.3
VDD1
VDD2
Si8422Bx
—
6.8
8.5
mA
—
6.8
8.5
VDD1
VDD2
Si8423Bx
—
6.8
8.5
mA
—
6.8
8.5
VDD1
VDD2
—
—
Timing Characteristics
3.4
9.2
5.1
11.5
mA
Si841xAx, Si842xAx
Maximum Data Rate
0
—
1.0 Mbps
Minimum Pulse Width
—
—
250
ns
Propagation Delay
tPHL, tPLH See Figure 1
—
Pulse Width Distortion
|tPLH - tPHL|
PWD
See Figure 1
—
Propagation Delay Skew2
tPSK(P-P)
—
Channel-Channel Skew
tPSK
—
Si841xBx, Si842xBx
—
35
ns
—
25
ns
—
40
ns
—
35
ns
Maximum Data Rate
0
—
150 Mbps
Minimum Pulse Width
—
—
6.0
ns
Propagation Delay
tPHL, tPLH See Figure 1
4.0
8.0
11
ns
Pulse Width Distortion
|tPLH - tPHL|
PWD
See Figure 1
—
1.5
3.0
ns
Propagation Delay Skew2
tPSK(P-P)
—
2.0
3.0
ns
Channel-Channel Skew
tPSK
—
0.5
1.5
ns
All Models
Output Rise Time
Output Fall Time
tr
CL = 15 pF
tf
CL = 15 pF
—
2.0
4.0
ns
—
2.0
4.0
ns
Peak Eye Diagram Jitter
tJIT(PK)
See Figure 6
—
350
—
ps
Common Mode Transient
Immunity
CMTI
VI = VDD or 0 V
20
45
— kV/µs
Start-up Time3
tSU
—
15
40
µs
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
6
Rev. 1.3
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