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SI8421AD Datasheet, PDF (14/37 Pages) List of Unclassifed Manufacturers – LOW-POWER, SINGLE AND DUAL-CHANNEL DIGITAL ISOLATORS
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA = –40 to 125 °C)
Parameter
Symbol Test Condition
Min
Typ
Max Unit
Si8422Bx
VDD1
VDD2
—
2.9
4.3
mA
—
2.9
4.3
Si8423Bx
VDD1
VDD2
—
3.4
5.1
mA
—
2.0
2.9
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
Si8420Bx
VDD1
VDD2
Si8421Bx
VDD1
VDD2
Si8422Bx
VDD1
VDD2
Si8423Bx
VDD1
VDD2
—
—
—
—
—
—
—
—
—
—
Timing Characteristics
2.0
3.0
mA
2.0
3.0
3.5
5.3
mA
5.5
6.9
4.6
5.8
mA
4.6
5.8
4.6
5.8
mA
4.6
5.8
3.4
5.1
mA
5.2
6.5
Si841xAx, Si842xAx
Maximum Data Rate
0
—
1.0 Mbps
Minimum Pulse Width
—
—
250
ns
Propagation Delay
tPHL, tPLH See Figure 1
—
Pulse Width Distortion
PWD
See Figure 1
—
|tPLH - tPHL|
Propagation Delay Skew3
tPSK(P-P)
—
Channel-Channel Skew
tPSK
—
Si841xBx, Si842xBx
—
35
ns
—
25
ns
—
40
ns
—
35
ns
Maximum Data Rate
0
—
150 Mbps
Notes:
1. Specifications in this table are also valid at VDD1 = 2.6 V and VDD2 = 2.6 V when the operating temperature range is
constrained to TA = 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
14
Rev. 1.3