LM3S808 Datasheet, PDF (58/416 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Offset Name
Type
Reset
Description
0x064
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x144
0x150
0x160
PLLCFG
RCGC0
RCGC1
RCGC2
SCGC0
SCGC1
SCGC2
DCGC0
DCGC1
DCGC2
DSLPCLKCFG
CLKVCLR
LDOARST
RO
-
XTAL to PLL Translation
R/W
0x00000040 Run Mode Clock Gating Control Register 0
R/W
0x00000000 Run Mode Clock Gating Control Register 1
R/W
0x00000000 Run Mode Clock Gating Control Register 2
R/W
0x00000040 Sleep Mode Clock Gating Control Register 0
R/W
0x00000000 Sleep Mode Clock Gating Control Register 1
R/W
0x00000000 Sleep Mode Clock Gating Control Register 2
R/W
0x00000040 Deep Sleep Mode Clock Gating Control Register 0
R/W
0x00000000 Deep Sleep Mode Clock Gating Control Register 1
R/W
0x00000000 Deep Sleep Mode Clock Gating Control Register 2
R/W
0x0780.0000 Deep Sleep Clock Configuration
R/W
0x0000.0000 Clock Verification Clear
R/W
0x0000.0000 Allow Unregulated LDO to Reset the Part
6.4 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
See
page
72
86
92
98
88
94
100
90
96
102
73
74
75
58
October 01, 2007
Preliminary