LM3S808 Datasheet, PDF (316/416 Pages) List of Unclassifed Manufacturers – Microcontroller

Synchronous Serial Interface (SSI)
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020
The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is
cleared. A write of 0 has no effect.
SSI Interrupt Clear (SSIICR)
SSI0 base: 0x4000.8000
Offset 0x020
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RTIC RORIC
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
W1C W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:2
1
Name
reserved
RTIC
Type
RO
W1C
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Receive Time-Out Interrupt Clear
The RTIC values are defined as follows:
Value Description
0 No effect on interrupt.
1 Clears interrupt.
0
RORIC
W1C
0
SSI Receive Overrun Interrupt Clear
The RORIC values are defined as follows:
Value Description
0 No effect on interrupt.
1 Clears interrupt.
316
October 01, 2007
Preliminary