LM3S808 Datasheet, PDF (15/416 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S808 Microcontroller
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 254
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 261
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 263
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 265
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 267
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 268
Register 6: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 269
Register 7: UART Control (UARTCTL), offset 0x030 ......................................................................... 271
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 272
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 274
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 276
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 277
Register 12: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 278
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 280
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 281
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 282
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 283
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 284
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 285
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 286
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 287
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 288
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 289
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 290
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 291
Synchronous Serial Interface (SSI) ............................................................................................ 292
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 304
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 306
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 308
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 309
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 311
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 312
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 314
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 315
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 316
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 317
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 318
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 319
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 320
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 321
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 322
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 323
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 324
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 325
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 326
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 327
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 328
October 01, 2007
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