LM3S808 Datasheet, PDF (179/416 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S808 Microcontroller
Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
reserved TBPWML TBOTE reserved
Type RO
R/W
R/W
RO
Reset
0
0
0
0
11
10
TBEVENT
R/W
R/W
0
0
9
8
7
6
5
4
TBSTALL TBEN reserved TAPWML TAOTE RTCEN
R/W
R/W
RO
R/W
R/W
R/W
0
0
0
0
0
0
19
18
17
16
RO
RO
RO
RO
0
0
0
0
3
2
1
0
TAEVENT
TASTALL TAEN
R/W
R/W
R/W
R/W
0
0
0
0
Bit/Field
31:15
14
Name
reserved
TBPWML
Type
RO
R/W
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
13
TBOTE
R/W
0
GPTM TimerB Output Trigger Enable
The TBOTE values are defined as follows:
Value Description
0 The output TimerB trigger is disabled.
1 The output TimerB trigger is enabled.
12
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
October 01, 2007
179
Preliminary