LM3S808 Datasheet, PDF (57/416 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S808 Microcontroller
2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN and OEN
bits in RCC. Setting the XTAL field automatically pulls valid PLL configuration data for the
appropriate crystal, and clearing the PWRDN and OEN bits powers and enables the PLL and its
output.
3. Select the desired system divider (SYSDIV) in RCC and set the USESYS bit in RCC. The SYSDIV
field determines the system frequency for the microcontroller.
4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register.
5. Enable use of the PLL by clearing the BYPASS bit in RCC.
Note: If the BYPASS bit is cleared before the PLL locks, it is possible to render the device unusable.
6.3 Register Map
Table 6-1 on page 57 lists the System Control registers, grouped by function. The offset listed is a
hexadecimal increment to the register’s address, relative to the System Control base address of
0x400F.E000.
Note: Spaces in the System Control register space that are not used are reserved for future or
internal use by Luminary Micro, Inc. Software should not modify any reserved memory
address.
Table 6-1. System Control Register Map
Offset Name
Type
Reset
Description
0x000 DID0
0x004 DID1
0x008 DC0
0x010 DC1
0x014 DC2
0x018 DC3
0x01C DC4
0x030 PBORCTL
0x034 LDOPCTL
0x040 SRCR0
0x044 SRCR1
0x048 SRCR2
0x050 RIS
0x054 IMC
0x058 MISC
0x05C RESC
0x060 RCC
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
RO
R/W
R/W1C
R/W
R/W
-
-
0x001F.001F
0x0001.32BF
0x0107.1013
0x3FFF.00C0
0x0000.001F
0x0000.7FFD
0x0000.0000
0x00000000
0x00000000
0x00000000
0x0000.0000
0x0000.0000
0x0000.0000
-
0x07A0.3AD1
Device Identification 0
Device Identification 1
Device Capabilities 0
Device Capabilities 1
Device Capabilities 2
Device Capabilities 3
Device Capabilities 4
Power-On and Brown-Out Reset Control
LDO Power Control
Software Reset Control 0
Software Reset Control 1
Software Reset Control 2
Raw Interrupt Status
Interrupt Mask Control
Masked Interrupt Status and Clear
Reset Cause
Run-Mode Clock Configuration
See
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October 01, 2007
57
Preliminary