LM3S617 Datasheet, PDF (55/379 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S617 Data Sheet
6
6.1
6.1.1
6.1.2
6.1.2.1
6.1.2.2
System Control
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
Functional Description
The System Control module provides the following capabilities:
„ Device identification, see page 55
„ Local control, such as reset (see page 55), power (see page 58) and clock control (see
page 58)
„ System control (Run, Sleep, and Deep-Sleep modes), see page 60
Device Identification
Seven read-only registers provide software with information on the microcontroller, such as
version, part number, SRAM size, Flash size, and other features. See the DID0, DID1 and
DC0-DC4 registers starting on page 63.
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
Reset Sources
The controller has six sources of reset:
1. External reset input pin (RST) assertion, see page 55.
2. Power-on reset (POR), see page 56.
3. Internal brown-out (BOR) detector, see page 56.
4. Software-initiated reset (with the software reset registers), see page 57.
5. A watchdog timer reset condition violation, see page 57.
6. Internal low drop-out (LDO) regulator output, see page 58.
After a reset, the Reset Cause (RESC) register (see page 82) is set with the reset cause. The bits
in this register are sticky and maintain their state across multiple reset sequences, except when an
external reset is the cause, and then all the other bits in the RESC register are cleared.
Note: The main oscillator is used for external resets and power-on resets; the internal oscillator
is used during the internal process by internal reset and clock verification circuitry.
RST Pin Assertion
The external reset pin (RST) resets the controller. This resets the core and all the peripherals
except the JTAG TAP controller (see “JTAG Interface” on page 45). The external reset sequence is
as follows:
1. The external reset pin (RST) is asserted and then de-asserted.
2. After RST is de-asserted, the main crystal oscillator must be allowed to settle and there is an
internal main oscillator counter that takes from 15-30 ms to account for this. During this time,
internal reset to the rest of the controller is held active.
May 4, 2007
55
Preliminary