LM3S617 Datasheet, PDF (211/379 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S617 Data Sheet
11.3.1
Module Initialization
Initialization of the ADC module is a simple process with very few steps. The main steps include
enabling the clock to the ADC and reconfiguring the Sample Sequencer priorities (if needed).
The initialization sequence for the ADC is as follows:
1. Enable the ADC clock by writing a value of 0x00010000 to the RCGC1 register in the System
Control module.
2. If required by the application, reconfigure the Sample Sequencer priorities in the ADCSSPRI
register. The default configuration has Sample Sequencer 0 with the highest priority, and
Sample Sequencer 3 as the lowest priority.
11.3.2
Sample Sequencer Configuration
Configuration of the Sample Sequencers is slightly more complex than the module initialization
since each sample sequence is completely programmable.
The configuration for each Sample Sequencer should be as follows:
1. Ensure that the Sample Sequencer is disabled by writing a 0 to the corresponding ASEN bit in
the ADCACTSS register. Programming of the Sample Sequencers is allowed without having
them enabled. Disabling the Sequencer during programming prevents erroneous execution if
a trigger event were to occur during the configuration process.
2. Configure the trigger event for the Sample Sequencer in the ADCEMUX register.
3. For each sample in the sample sequence, configure the corresponding input source in the
ADCSSMUXn register.
4. For each sample in the sample sequence, configure the sample control bits in the
corresponding nibble in the ADCSSCTLn register. When programming the last nibble, ensure
that the END bit is set. Failure to set the END bit causes unpredictable behavior.
5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register.
6. Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the
ADCACTSS register.
11.4
Register Map
Table 11-2 lists the ADC registers. The offset listed is a hexadecimal increment to the register’s
address, relative to the ADC base address of 0x40038000.
Table 11-2. ADC Register Map
Offset Name
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
ADCACTSS
ADCRIS
ADCIM
ADCISC
ADCOSTAT
ADCEMUX
ADCUSTAT
Reset
Type Description
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
R/W Active sample sequencer
RO Raw interrupt status and clear
R/W Interrupt mask
R/W1C Interrupt status and clear
R/W1C Overflow status
R/W Event multiplexer select
R/W1C Underflow status
See
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May 4, 2007
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Preliminary