LM3S617 Datasheet, PDF (153/379 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S617 Data Sheet
9.1 Block Diagram
Figure 9-1. GPTM Module Block Diagram
Interrupt / Config
TimerA
Interrupt
TimerB
Interrupt
GPTMCFG
GPTMCTL
GPTMIMR
GPTMRIS
GPTMMIS
GPTMICR
TimerA Control
GPTMTAPMR
GPTMTAPR
GPTMTAMATCHR
GPTMTAILR
GPTMTAMR
TimerB Control
GPTMTBPMR
GPTMTBPR
GPTMTBMATCHR
GPTMTBILR
GPTMTBMR
0x0000 (Down Counter Modes )
TA Comparator
GPTMAR En
GPTMTBR En
TB Comparator
Clock / Edge
Detect
CCP (even)
RTC Divider
Clock / Edge
Detect
CCP (odd)
9.2
9.2.1
9.2.2
System
Clock
0x0000 (Down Counter Modes )
Functional Description
The main components of each GPTM block are two free-running 16-bit up/down counters (referred
to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two
16-bit load/initialization registers and their associated control functions. The exact functionality of
each GPTM is controlled by software and configured through the register interface.
Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see
page 164), the GPTM TimerA Mode (GPTMTAMR) register (see page 165), and the GPTM
TimerB Mode (GPTMTBMR) register (see page 166). When in one of the 32-bit modes, the timer
can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its
two 16-bit timers configured in any combination of the 16-bit modes.
GPTM Reset Conditions
After reset has been applied to the GPTM module, the module is in an inactive state, and all
control registers are cleared and in their default states. Counters TimerA and TimerB are initialized
to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load
(GPTMTAILR) register (see page 174) and the GPTM TimerB Interval Load (GPTMTBILR)
register (see page 175). The prescale counters are initialized to 0x00: the GPTM TimerA
Prescale (GPTMTAPR) register (see page 178) and the GPTM TimerB Prescale (GPTMTBPR)
register (see page 179).
32-Bit Timer Operating Modes
Note: Both the odd- and even-numbered CCP pins are used for 16-bit mode. Only the
even-numbered CCP pins are used for 32-bit mode.
May 4, 2007
153
Preliminary