LM3S617 Datasheet, PDF (167/379 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S617 Data Sheet
Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
GPTM Control (GPTMCTL)
Offset 0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
res TBPWML TBOTE res
Type
RO
R/W
R/W
RO
Reset
0
0
0
0
TBEVENT
R/W
R/W
0
0
TBSTALL TBEN
R/W
R/W
0
0
res TAPWML TAOTE RTCEN
RO
R/W
R/W
R/W
0
0
0
0
TAEVENT
R/W
R/W
0
0
TASTALL TAEN
R/W
R/W
0
0
Bit/Field
31:15
14
13
12
11:10
9
8
7
Name
reserved
TBPWML
TBOTE
reserved
TBEVENT
TBSTALL
TBEN
reserved
Type
RO
R/W
R/W
RO
R/W
R/W
R/W
RO
Reset
0
0
0
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should never
be changed.
GPTM TimerB PWM Output Level
0: Output is unaffected.
1: Output is inverted.
GPTM TimerB Output Trigger Enable
0: The output TimerB trigger is disabled.
1: The output TimerB trigger is enabled.
Reserved bits return an indeterminate value, and should never
be changed.
GPTM TimerB Event Mode
00: Positive edge.
01: Negative edge.
10: Reserved.
11: Both edges.
GPTM TimerB Stall Enable
0: TimerB stalling is disabled.
1: TimerB stalling is enabled.
GPTM TimerB Enable
0: TimerB is disabled.
1: TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
Reserved bits return an indeterminate value, and should never
be changed.
May 4, 2007
167
Preliminary