LM3S617 Datasheet, PDF (342/379 Pages) List of Unclassifed Manufacturers – Microcontroller

Pulse Width Modulator (PWM)
Register 18: PWM0 Generator A Control (PWM0GENA), offset 0x060
control the generation of the PWMNA signal based on the load and zero output pulses from the
counter, as well as the compare A and compare B pulses from the comparators. When the counter
is running in Count-Down mode, only four of these events occur; when running in Count-Up/Down
mode, all six occur. These events provide great flexibility in the positioning and duty cycle of the
PWM signal that is produced.
The PWM0GENA register controls generation of the PWM0A signal.
Each field can take on one of the values defined in Table 15-2, which defines the effect of the
event on the output signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare A action is taken and the compare B action is ignored.
PWMn Generator A Control (PWMnGENA)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
ActCmpBD
ActCmpBU
ActCmpAD
ActCmpAU
ActLoad
ActZero
Type
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:12
Name
reserved
11:10
ActCmpBD
9:8
ActCmpBU
Type
RO
R/W
R/W
7:6
ActCmpAD
R/W
5:4
ActCmpAU
R/W
3:2
ActLoad
R/W
1:0
ActZero
R/W
Reset
0
0
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
The action to be taken when the counter matches
comparator B while counting down.
The action to be taken when the counter matches
comparator B while counting up. Occurs only when the
Mode bit in the PWMnCTL register (see page 334) is set
to 1.
The action to be taken when the counter matches
comparator A while counting down.
The action to be taken when the counter matches
comparator A while counting up.Occurs only when the
Mode bit in the PWMnCTL register is set to 1.
The action to be taken when the counter matches the load
value.
The action to be taken when the counter is zero.
342
May 4, 2007
Preliminary