LM3S617 Datasheet, PDF (217/379 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S617 Data Sheet
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
This register indicates overflow conditions in the Sample Sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.
ADC Overflow Status (ADCOSTAT)
Offset 0x010
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
OV3 OV2 OV1 OV0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W1C
R/W1C
R/W1C
R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
2
1
0
Name
reserved
OV3
OV2
OV1
OV0
Type
RO
R/W1C
R/W1C
R/W1C
R/W1C
Reset
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
This bit specifies that the FIFO for Sample Sequencer 3 has
hit an overflow condition where the FIFO is full and a write
was requested. When an overflow is detected, the most
recent write is dropped and this bit is set by hardware to
indicate the occurrence of dropped data. This bit is cleared by
writing a 1.
This bit specifies that the FIFO for Sample Sequencer 2 has
hit an overflow condition where the FIFO is full and a write
was requested. When an overflow is detected, the most
recent write is dropped and this bit is set by hardware to
indicate the occurrence of dropped data. This bit is cleared by
writing a 1.
This bit specifies that the FIFO for Sample Sequencer 1 has
hit an overflow condition where the FIFO is full and a write
was requested. When an overflow is detected, the most
recent write is dropped and this bit is set by hardware to
indicate the occurrence of dropped data. This bit is cleared by
writing a 1.
This bit specifies that the FIFO for Sample Sequencer 0 has
hit an overflow condition where the FIFO is full and a write
was requested. When an overflow is detected, the most
recent write is dropped and this bit is set by hardware to
indicate the occurrence of dropped data. This bit is cleared by
writing a 1.
May 4, 2007
217
Preliminary