LM3S617 Datasheet, PDF (337/379 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S617 Data Sheet
Register 13: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C
provide the current set of interrupt sources that are asserted to the controller. Bits set to 1 indicate
the latched events that have occurred; a 0 bit indicates that the event in question has not occurred.
These are R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt reason.
PWMn Interrupt Status (PWMnISC)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
Name
reserved
Type
RO
5
IntCmpBD
R/W1C
4
IntCmpBU
R/W1C
3
IntCmpAD
R/W1C
2
IntCmpAU
R/W1C
1
IntCntLoad
R/W1C
0
IntCntZero
R/W1C
Reset
0
0
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
Indicates that the counter has matched the comparator B
value while counting down.
Indicates that the counter has matched the comparator B
value while counting up.
Indicates that the counter has matched the comparator A
value while counting down.
Indicates that the counter has matched the comparator A
value while counting up.
Indicates that the counter has matched the PWMnLOAD
register.
Indicates that the counter has matched 0.
May 4, 2007
337
Preliminary