LM3S1958 Datasheet, PDF (356/435 Pages) List of Unclassifed Manufacturers – Microcontroller

Inter-Integrated Circuit (I²C) Interface
15.2.1.5 Arbitration
A master may start a transfer only if the bus is idle. Its possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is high. During arbitration, the first of the
competing master devices to place a '1' (high) on SDA while another master transmits a '0' (low)
will switch off its data output stage and retire until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
15.2.2
Available Speed Modes
The I²C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP.
where:
CLK_PRD is the system clock period
SCL_LP is the low phase of SCL (fixed at 6)
SCL_HP is the high phase of SCL (fixed at 4)
TIMER_PRD is the programmed value in the I²C Master Timer Period (I2CMTPR) register (see
page 373).
The I²C clock period is calculated as follows:
SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD
For example:
CLK_PRD = 50 ns
TIMER_PRD = 2
SCL_LP=6
SCL_HP=4
yields a SCL frequency of:
1/T = 333 Khz
Table 15-1 on page 356 gives examples of Timer period, system clock, and speed mode (Standard
or Fast).
Table 15-1. Examples of I²C Master Timer Period versus Speed Mode
System Clock Timer Period Standard Mode Timer Period Fast Mode
4 Mhz
0x01
100 Kbps
-
-
6 Mhz
0x02
100 Kbps
-
-
12.5 Mhz
0x06
89 Kbps
0x01
312 Kbps
16.7 Mhz
0x08
93 Kbps
0x02
278 Kbps
20 Mhz
0x09
100 Kbps
0x02
333 Kbps
25 Mhz
0x0C
96.2 Kbps
0x03
312 Kbps
33Mhz
0x10
97.1 Kbps
0x04
330 Kbps
40Mhz
0x13
100 Kbps
0x04
400 Kbps
356
June 14, 2007
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