LM3S1958 Datasheet, PDF (15/435 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S1958 Microcontroller
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 258
ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 259
ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 260
ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 261
ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 262
ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 264
ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 266
ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 266
ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 266
ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 267
ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 267
ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................. 267
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 268
ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 269
ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 270
ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 271
ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 272
ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 273
ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 274
ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 275
ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 276
UART ............................................................................................................................................. 278
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 286
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 288
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 290
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 292
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 293
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 294
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 295
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 297
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 299
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 300
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 302
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 303
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 304
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 306
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 307
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 308
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 309
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 310
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 311
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 312
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 313
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 314
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 315
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 316
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 317
June 14, 2007
15
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