LM3S1958 Datasheet, PDF (16/435 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
SSI ................................................................................................................................................. 318
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 330
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 332
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 334
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 335
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 336
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 337
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 338
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 339
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 340
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 341
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 342
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 343
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 344
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 345
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 346
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 347
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 348
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 349
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 350
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 351
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 352
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 353
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 367
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 368
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 372
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 373
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 374
Register 6: I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 375
Register 7: I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 376
Register 8: I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 377
Register 9: I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 378
Register 10: I²C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 380
Register 11: I²C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 381
Register 12: I²C Slave Data (I2CSDR), offset 0x008 ........................................................................... 383
Register 13: I²C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 384
Register 14: I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 385
Register 15: I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 386
Register 16: I²C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 387
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June 14, 2007
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