LM3S1958 Datasheet, PDF (27/435 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S1958 Microcontroller
1.4.3
1.4.3.1
1.4.3.2
1.4.3.3
On the LM3S1958, PWM motion control functionality can be achieved through the motion control
features of the general-purpose timers (using the CCP pins).
CCP Pins (see page 195)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
Serial Communications Peripherals
The LM3S1958 controller supports both asynchronous and synchronous serial communications
with:
■ Three fully programmable 16C550-type UARTs
■ Two SSI modules
■ Two I²C modules
UART (see page 278)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S1958 controller includes three fully programmable 16C550-type UARTs that support data
transfer speeds up to 460.8 Kbps. In addition, each UART is capable of supporting IrDA. (Although
similar in functionality to a 16C550 UART, it is not register-compatible.)
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
SSI (see page 318)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S1958 controller includes two SSI modules that provide the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE , or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
Each SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
Each SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
Each SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
I²C(see page 353)
The Inter-Integrated Circuit (I²C) bus provides bi-directional data transfer through a two-wire design
(a serial data line SDA and a serial clock line SCL).
June 14, 2007
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