C8051F340 Datasheet, PDF (29/282 Pages) List of Unclassifed Manufacturers – Full Speed USB Flash MCU Family

C8051F340/1/2/3/4/5/6/7
1.10. Comparators
C8051F340/1/2/3/4/5/6/7 devices include two on-chip voltage comparators that are enabled/disabled and
configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux.
Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asyn-
chronous) output. Comparator response time is programmable, allowing the user to select between
high-speed and low-power modes. Positive and negative hysteresis are also configurable.
Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these inter-
rupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source.
Figure 1.10 shows the Comparator0 block diagram.
CMXnN2
CMXnN1
CMXnN0
CMXnP2
CMXnP1
CMXnP0
CPnEN
CPnOUT
CPnRIF
CPnFIF
CPnHYP1
CPnHYP0
CPnHYN1
CPnHYN0
CPn +
CPn -
VDD
CPn
Interrupt
+
-
GND
CPn
Rising-edge
CPn
Falling-edge
D ^SET Q
Q CLR
D ^SET Q
Q CLR
(SYNCHRONIZER)
Interrupt
Logic
CPnRIE
CPnFIE
CPn
Crossbar
CPnA
Port I/O connection options vary with
package (32-pin or 48-pin)
CPnRIE
CPnFIE
Reset Decision Tree
(Comprator 0 Only)
CPnMD1
CPnMD0
Figure 1.10. Comparator0 Block Diagram
Rev. 0.5
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