C8051F340 Datasheet, PDF (28/282 Pages) List of Unclassifed Manufacturers – Full Speed USB Flash MCU Family

C8051F340/1/2/3/4/5/6/7
1.9. 10-Bit Analog to Digital Converter
The C8051F340/1/2/3/4/5/6/7 devices include an on-chip 10-bit SAR ADC with a true differential input mul-
tiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL of ±1LSB.
The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC
inputs. Twenty (48-pin package) or twenty-one (32-pin package) of the Port I/O pins can be used as analog
inputs to the ADC. Additionally, the on-chip Temperature Sensor output and the power supply voltage
(V_DD) are available as ADC inputs. User firmware may shut down the ADC to save power.
Conversions can be started in six ways: a software command, an overflow of Timer 0, 1, 2, or 3, or an
external convert start signal. This flexibility allows the start of conversion to be triggered by software
events, a periodic signal (timer overflows), or external HW signals. Conversion completions are indicated
by a status bit and an interrupt (if enabled). The resulting 10-bit data word is latched into the ADC data
SFRs upon completion of a conversion.
Window compare registers for the ADC output data can be configured to interrupt the controller when ADC
data is either within or outside of a specified range. The ADC can monitor a key voltage continuously in
background mode, but not interrupt the controller unless the converted data is within/outside the specified
range.
Analog Multiplexer
* 21 Selections on 32-pin package
20 Selections on 48-pin package
Port I/O
Pins*
VDD
Temp
Sensor
Positive
Input
(AIN+)
AMUX
Port I/O
Pins*
VREF
GND
Negative
Input
(AIN-)
AMUX
Configuration, Control, and Data Registers
000
Start
Conversion ⁰⁰¹
010
011
100
101
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 1 Overflow
CNVSTR Input
Timer 3 Overflow
10-Bit
(+)
SAR
(-)
ADC
ADC Data
16
Registers
End of
Conversion
Interrupt
Window Compare
Logic
Window
Compare
Interrupt
Figure 1.9. 10-Bit ADC Block Diagram
28
Rev. 0.5